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S9S08SG16E1VTGR Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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S9S08SG16E1VTGR Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 328 page  Chapter 6 Parallel Input/Output Control MC9S08SG32 Data Sheet, Rev. 7 86 Freescale Semiconductor 6.6.2.3 Port B Pull Enable Register (PTBPE) NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured to detect rising edges. 6.6.2.4 Port B Slew Rate Enable Register (PTBSE) 76543210 R PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 W Reset: 00000000 Figure 6-13. Internal Pull Enable for Port B Register (PTBPE) Table 6-12. PTBPE Register Field Descriptions Field Description 7:0 PTBPE[7:0] Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port B bit n. 1 Internal pull-up/pull-down device enabled for port B bit n. 76543210 R PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 W Reset: 00000000 Figure 6-14. Slew Rate Enable for Port B Register (PTBSE) Table 6-13. PTBSE Register Field Descriptions Field Description 7:0 PTBSE[7:0] Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. |
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