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MC33596 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

Part No. MC33596
Description  PLL Tuned UHF Receiver for Data Transfer Applications
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC33596 Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc

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MC33596 Data Sheet, Rev. 4
Register Description
Freescale Semiconductor
36
Low-pass data filter
Low-pass average filter generating the data slicer reference, if DSREF is set
Data manager
If the data manager is disabled, the incoming signal data rate must be lower than or equal to the data
manager maximum data rate.
TRXE (Receiver Enable) enables the whole receiver. This bit must be set to high level if MCU wakes the
MC33956 to enter receive mode.
0 = standby mode
1 = other modes can be activated
DME (Data Manager Enable) enables the data manager.
0 = disabled
1 = enabled
SOE (Strobe Oscillator Enable) enables the strobe oscillator.
0 = disabled
1 = enabled
Figure 26 describes configuration register 3, CONFIG3.
OLS (Out of Lock Status) indicates the current status of the PLL.
0 = The PLL is in lock-in range
1 = The PLL is out of lock-in range
LVDS (Low Voltage Detection Status) indicates that a low voltage event has occurred when LVDE = 1.
This bit is read-only and is cleared after a read access.
0 = No low voltage detected
1 = Low voltage detected
ILA[1:0] (Input Level Attenuation) define the RF input level attenuation.
Table 10. Base Band Parameter Configuration
DR1
DR0
Data Filter
Cut-off Frequency
Average Filter
Cut-off Frequency
Data Manager
Data Rate Range
0
0
6 kHz
0.5 kHz
2–2.8 kBd
0
1
12 kHz
1 kHz
4–5.6 kBd
1
0
24 kHz
2 kHz
8–10.6 kBd
1
1
48 kHz
4 kHz
16–22.4 kBd
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
AFF1
AFF0
OLS
LVDS
ILA1
ILA0
$02
Reset Value
0
0
1
1
0
0
0
0
Access
R/W
R/W
R
R
R/W
R/W
Figure 26. CONFIG3 Register


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