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MC33596 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

Part No. MC33596
Description  PLL Tuned UHF Receiver for Data Transfer Applications
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC33596 Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc

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Register Description
MC33596 Data Sheet, Rev. 4
Freescale Semiconductor
35
LVDE (Low Voltage Detection Enable) enables the low voltage detection function.
0 = disabled
1 = enabled
NOTE
This bit is cleared by POR. In the event of a complete loss of the supply
voltage, LVD is disabled at power-up, but the information is not lost as the
status bit LVDS is set by POR.
CLKE (Clock Enable) controls the DATACLK output buffer.
0 = DATACLK remains low
1 = DATACLK outputs Fdataclk
Figure 25 describes configuration register 2, CONFIG2.
DSREF (Data Slicer Reference) selects the data slicer reference.
0 = Fixed reference (cannot be used in FSK)
1 = Adaptive reference (recommended for maximum sensitivity in OOK and FSK)
In the case of FSK modulation (MODU = 1), DSREF must be set.
FRM (Frequency Register Manager) enables either a user friendly access to one frequency register or a
direct access to the two frequency registers.
0 = The carrier frequency and the FSK deviation are defined by the F register
1 = The local oscillator frequency and the two carrier frequencies are defined by two frequency
registers, F and FT.
MODU (Modulation) sets the data modulation type.
0 = On/Off Keying (OOK) modulation
1 = Frequency Shift Keying (FSK) modulation
DR[1:0] (Data Rate) configure the receiver blocks operating in base band.
Table 9. Active Level of SWITCH Output Pin
SL
Receiver Function
Level on SWITCH
0
Receiving
Low
High
1—
Low
Receiving
High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
DSREF
FRM
MODU
DR1
DR0
TRXE
DME
SOE
$01
Reset Value
0
0
0
1
0
0
0
0
Access
R/WR/W
R/WR/W
R/WR/W
R/W
R/W
Figure 25. CONFIG2 Register


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