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IMX51 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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IMX51 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 184 page  i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 8 Freescale Semiconductor Preliminary—Subject to Change Without Notice Features IIM IC Identification Module Security The IC Identification Module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. IOMUXC IOMUX Control System Control Peripherals This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. IPU Image Processing Unit Multimedia Peripherals IPU enables connectivity to displays and image sensors, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces. • Legacy Interfaces • Analog TV interfaces (through a TV encoder bridge) The processing includes: • Support for camera control • Image enhancement: color adjustment and gamut mapping, gamma correction and contrast enhancement, sharpening and noise reduction • Video/graphics combining • Support for display backlight reduction • Image conversion—resizing, rotation, inversion and color space conversion • Synchronization and control capabilities, allowing autonomous operation. • Hardware de-interlacing support KPP Keypad Port Connectivity Peripherals The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection P-ATA (Muxed with eSDHC-4 Parallel ATA Connectivity Peripherals The P-ATA block is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives. It interfaces with the ATA-5 (UDMA-4) compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. This is muxed with eSDHC-4 interfaces. PWM-1 PWM-2 Pulse Width Modulation Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound. RAM 128 Kbytes Internal RAM Internal Memory Unified RAM, can be split between Secure RAM and Non-Secure RAM ROM 36 Kbytes Boot ROM Internal Memory Supports secure and regular Boot Modes Table 2. i.MX51 Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description |
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