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SPC5643LF0VMM8 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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SPC5643LF0VMM8 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 98 page  Overview MPC5643L Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor 7 1.3 Feature details 1.3.1 High-performance e200z4d core The e200z4d Power Architecture™ core provides the following features: • Two independent execution units, both supporting fixed-point and floating-point operations • Dual issue 32-bit Power Architecture™ (Book E) compliant — Five-stage pipeline (IF, DEC, EX1, EX2, WB) — In-order execution and instruction retirement • Full support for Power Architecture instruction set and Variable Length Encoding (VLE) — Mix of classic 32-bit and 16-bit instruction allowed — Optimization of code size possible • Thirty-two 64-bit general purpose registers (GPRs) • Harvard bus (32-bit address, 64-bit data) — I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return — D-Bus interface capable of two transactions outstanding to fill AHB pipe • I-cache and I-cache controller — 4 KB, 256-bit cache line (programmable for 2- or 4-way) • No data cache • 16-entry MMU • 8-entry branch table buffer • Branch look-ahead instruction buffer to accelerate branching • Dedicated branch address calculator • Three cycles worst case for missed branch • Load/store unit — Fully pipelined — Single-cycle load latency — Big- and little-endian modes supported — Misaligned access support — Single stall cycle on load to use • Single-cycle throughput (two-cycle latency) integer 32 × 32 multiplication • 4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles) • Single precision floating-point unit — 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication — Target nine cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division — Special square root and min/max function implemented • Signal processing support: APU-SPE 1.1 — Support for vectorized mode: as many as two floating-point instructions per clock • Vectored interrupt support • Reservation instruction to support read-modify-write constructs • Extensive system development and tracing support via Nexus debug port |
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