MPL115A2

Sensors

4

Freescale Semiconductor

Pressure

Coefficient Bit-Width Specs

The table below specifies the initial coefficient bit-width specs for the compensation algorithm.

* Factory reserves the option to make these values = 0.

Example Binary Format Definitions:

1.

Sign = 0, Integer Bits = 8, Fractional Bits = 4 :

2.

Sign = 1, Integer Bits = 4, Fractional Bits = 7 :

3.

4.

NOTE: Negative coefficients (Sign = 1) are coded in 2’s complement notation.

Coefficient Address Map

For coefficients with less than 16 bits, the lower lsbs are zero. For example, c11 is 11 bits and is stored into 2 bytes as follows:

10-bit Output: Compensation Coefficient Specs

Total

Coeff.

Bits

a0

b1

b2

c12

c11*

c22*

Total Bits

16

16

16

14

11

11

84

Sign Bits

1

1

1

1

1

1

Integer Bits

12

2

1

0

0

0

Fractional Bits

4

13

14

13

11

10

dec pt zero pad

—

—

—

9

11

15

Address

Coefficient

$04

a0 MS Byte

$05

a0 LS Byte

$06

b1 MS Byte

$07

b1 LS Byte

$08

b2 MS Byte

$09

b2 LS Byte

$0A

c12 MS Byte

$0B

c12 LS Byte

$0C

c11 MS Byte

$0D

c11 LS Byte

$0E

c22 MS Byte

$0F

c22 LS Byte