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MPC5602BEVLL Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MPC5602BEVLL Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 72 page MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 Device blocks Freescale Semiconductor 6 2.2 Device block summary Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 2. MPC5604B/C series block summary Block Function Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock generation module (CGM) Provides logic and control required for the generation of system and peripheral clocks Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINflex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Non-Maskable Interrupt (NMI) Handles external events that must produce an immediate response, such as power down detection Nexus development interface (NDI) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard |
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