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UJA1069TW24 Datasheet(PDF) 3 Page - NXP Semiconductors |
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UJA1069TW24 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 64 page UJA1069_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 28 October 2009 3 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip 2.4 Fail-safe features I Safe and predictable behavior under all conditions I Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision I Fail-safe coded 16-bit SPI interface for the microcontroller I Global enable pin for the control of safety-critical hardware I Detection and detailed reporting of failures: N On-chip oscillator failure and watchdog alerts N Battery and voltage regulator undervoltages N LIN-bus failures (short-circuits) N TXDL and RXDL clamping situations and short-circuits N Clamped or open reset line N SPI message errors N Overtemperature warning I Rigorous error handling based on diagnostics I Supply failure early warning allows critical data to be stored I 23 bits of access-protected RAM is available e.g. for logging of cyclic problems I Reporting in a single SPI message; no assembly of multiple SPI frames needed I Limp-home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights) I Fail-safe coded activation of Software development mode and Flash mode I Unique SPI readable device type identification I Software-initiated system reset 3. Ordering information Table 1. Ordering information Type number Package Name Description Version UJA1069TW HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 UJA1069TW24 HTSSOP24 plastic thermal enhanced thin shrink small outline package; 24 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed die pad SOT864-1 |
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