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TDA8922C Datasheet(PDF) 12 Page - NXP Semiconductors

Part No. TDA8922C
Description  2 X 75 W class-D power amplifier
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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TDA8922C Datasheet(HTML) 12 Page - NXP Semiconductors

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TDA8922C_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 7 September 2009
12 of 40
NXP Semiconductors
TDA8922C
2
× 75 W class-D power amplifier
Stereo operation: to avoid acoustical phase differences, the inputs should be in
anti-phase and the speakers should be connected in anti-phase. This configuration:
– minimizes power supply peak current
– minimizes supply pumping effects, especially at low audio frequencies
Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the
TDA8922C. In practice (because of the OCP threshold) the output power can be
boosted to twice the output power that can be achieved with the single-ended
configuration.
The input configuration for a mono BTL application is illustrated in Figure 7.
9.
Limiting values
Fig 7.
Input configuration for mono BTL application
Vin
IN1P
OUT1
power stage
mbl466
OUT2
SGND
IN1M
IN2P
IN2M
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
∆V
voltage difference
VDD − VSS; Standby, Mute modes
-
65
V
IORM
repetitive peak output current
maximum output current limiting
6
-
A
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
-
150
°C
VMODE
voltage on pin MODE
referenced to SGND
0
6
V
VOSC
voltage on pin OSC
0
SGND + 6
V
VI
input voltage
referenced to SGND
pins IN1P, IN1M, IN2P and IN2M
−5+5
V
VPROT
voltage on pin PROT
referenced to voltage on pin VSSD
0
12
V
VESD
electrostatic discharge voltage
Human Body Model (HBM)
−2000 +2000
V
Charged Device Model (CDM)
−500
+500
V
Iq(tot)
total quiescent current
Operating mode; no load; no filter
no RC-snubber network connected
-70
mA
VPWM(p-p)
peak-to-peak PWM voltage
on pins OUT1 and OUT2
-
120
V


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