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PCF8576DT/2 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCF8576DT/2 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 52 page PCF8576D_9 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 — 25 August 2009 8 of 52 NXP Semiconductors PCF8576D Universal LCD driver for low multiplex rates The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. 7.1 Power-on reset At power-on the PCF8576D resets to the following starting conditions: • All backplane outputs are set to VLCD • All segment outputs are set to VLCD • The selected drive mode is: 1:4 multiplex with 1 ⁄ 3 bias • Blinking is switched off • Input and output bank selectors are reset • The I2C-bus interface is initialized • The data pointer and the subaddress counter are cleared (set to logic 0) • Display is disabled Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 1 ⁄ 2 bias voltage level for the 1:2 multiplex configuration. The LCD voltage can be temperature compensated externally using the supply to pin VLCD. The resistance of the power lines must be kept to a minimum. For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately between the chip and the connector. Fig 5. Typical system configuration HOST MICRO- PROCESSOR/ MICRO- CONTROLLER tr 2CB SDA SCL OSC 40 segment drives 4 backplanes LCD PANEL (up to 160 elements) PCF8576D A0 A1 A2 SA0 VDD VSS VSS VDD VLCD mdb079 R ≤ |
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