HM5212165FLTD-75 datasheet(33/62 Pages) ELPIDA

Part #	HM5212165FLTD-75

Description	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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33 / 62 page

HM5212165FLTD/HM5212805FLTD-75/A60/B60

Data Sheet E0180H10

33

Read command to Precharge command interval (same bank):

When the precharge command is executed for the same bank as the read command that preceded it, theminimum

interval between the two commands is one clock. However, since the output buffer then becomes High-Z after

the clocks defined by l

HZP, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the

precharge command is input during burst read. To read all data by burst read, the clocks defined by l

EP must be

assured as an interval from the final data output to precharge command execution.

READ to PRECHARGE Command Interval (same bank): To output all data

CAS Latency = 2, Burst Length = 4

CLK

Command

Dout

READ

PRE/PALL

out A0

out A1

out A2

out A3

CL=2

l

= -1 cycle

EP

CAS Latency = 3, Burst Length = 4

CLK

Command

Dout

READ

PRE/PALL

out A0

out A1

out A2

out A3

CL=3

l

= -2 cycle

EP

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HM5212165FLTD-75 Datasheet(PDF) 33 Page - Elpida Memory

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