HM5212165FLTD-75 datasheet(27/62 Pages) ELPIDA

Part #	HM5212165FLTD-75

Description	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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27 / 62 page

HM5212165FLTD/HM5212805FLTD-75/A60/B60

Data Sheet E0180H10

27

Write command to Write command interval:

1. Same bank, same ROW address: When another write command is executed at the same ROW address of

the same bank as the preceding write command, the second write can be performed after an interval of no less

than 1 clock. In the case of burst writes, the second write command has priority.

WRITE to WRITE Command Interval (same ROW address in same bank)

CLK

Command

Din

in B3

Address

in B1

in B2

BS

ACTV

Row

Column A

WRIT

Column B

in A0

in B0

Bank0

Active

Column =A

Write

Column =B

Write

Burst Write Mode

Burst Length = 4

Bank 0

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands

cannot be executed; it is necessary to separate the two write commands with a precharge command and a

bank-active command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less than

1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second write

command has priority.

WRITE to WRITE Command Interval (different bank)

CLK

Command

Din

in B3

Address

in B1

in B2

BS

ACTV

Row 0

Row 1

ACTV

WRIT

Column A

in A0

in B0

Bank0

Active

Bank3

Active

Bank0

Write

Bank3

Write

WRIT

Column B

Burst Write Mode

Burst Length = 4

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Hitachi Semiconductor	HM5212165FLTD-75	859Kb / 63P	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM

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HM5212165FLTD-75 Datasheet(PDF) 27 Page - Elpida Memory

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