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EDX5116ACSE-3C-E Datasheet(PDF) 58 Page - Elpida Memory |
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EDX5116ACSE-3C-E Datasheet(HTML) 58 Page - Elpida Memory |
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58 / 78 page  Preliminary Data Sheet E0881E20 (Ver. 2.0) 58 EDX5116ACSE Operating Conditions Electrical Conditions Table 12 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory compo- nent. The first section of parameters is concerned with abso- lute voltages, storage, and operating temperatures, and the power supply, reference, and termination voltages. The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF,RSL. The third section of parameters determines the input voltage levels for the RSL SI (serial interface) signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF,RSL. The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are specified by a common-mode value and a swing value. The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and low voltage are specified by a common-mode value and a swing value. Table 12 Electrical Conditions Symbol Parameter Minimum Maximum Unit VIN,ABS Voltage applied to any pin (except VDD) with respect to GND - 0.300 1.500 V VDD,ABS Voltage on VDD with respect to GND - 0.500 2.300 V TSTORE Storage temperature - 50 100 °C TJ Junction temperature under bias during normal operation 0 100 °C VDD Supply voltage applied to VDD pins during normal operation 1.800 - 0.090 1.800 + 0.090 V VREF,RSL RSL - Reference voltage applied to VREF pina VTERM,RSL - 0.450 - 0.025 VTERM,RSL - 0.450 + 0.025 V VTERM,DRSL DRSL - Termination voltage applied to VTERM pins 1.200 - 0.060 1.200 + 0.060 V VIL,RQ RSL RQ inputs -low voltage VREF,RSL - 0.450 VREF,RSL - 0.150 V VIH,RQb RSL RQ inputs -high voltage VREF,RSL + 0.150 VREF,RSL + 0.450 V RA,RQ RSL RQ inputs - data asymmetry: RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ) 0.8 1.2 - VIL,SI RSL Serial Interface inputs -low voltage VREF,RSL - 0.450 VREF,RSL - 0.200 V VIH,SIb RSL Serial Interface inputs -high voltage VREF,RSL + 0.200 VREF,RSL + 0.450 V RA,SI RSL Serial Interface inputs - data asymmetry: RA,SI = (VIH,SI-VREF,RSL)/(VREF,RSL-VIL,SI) 0.8 1.2 - VICM,CFM CFM/CFMN input - common mode: VICM,CFM = (VIH,CFMb+VIL,CFM)/2 VTERM,DRSL - 0.150 VTERM,DRSL - 0.075 V VISW,CFM CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CFMb - VIL,CFM) 0.150 0.300 V VICM,DQ DRSL DQ inputs - common mode: VICM,DQ = (VIH,DQb+VIL,DQ)/2 VTERM,DRSL-0.150 VTERM,DRSL-0.025 V VISW,DQ DRSL DQ inputs - high-low swing: VISW,DQ = (VIH,DQb - VIL,DQ) 0.050 0.300 V a. VTERM,RSL is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component. b. VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system. |
Similar Part No. - EDX5116ACSE-3C-E |
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Similar Description - EDX5116ACSE-3C-E |
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