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EDE1116ACSE-8E-E Datasheet(PDF) 31 Page - Elpida Memory |
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EDE1116ACSE-8E-E Datasheet(HTML) 31 Page - Elpida Memory |
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31 / 82 page  EDE1104ACSE, EDE1108ACSE, EDE1116ACSE Data Sheet E0975E50 (Ver.5.0) 31 CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and Self-Refresh operation (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power down entry and exit, and for self-refresh entry. CKE is asynchronous for self-refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self- refresh. DM, UDM and LDM (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by EMRS. In × 16 configuration, UDM controls upper byte (DQ8 to DQ15) and LDM controls lower byte (DQ0 to DQ7). In this datasheet, DM represents UDM and LDM. DQ (input/output pins) Bi-directional data bus. DQS, /DQS UDQS, /UDQS, LDQS, /LDQS (input/output pins) Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, centered in write data. Used to capture write data. /DQS can be disabled by EMRS. In × 16 configuration, UDQS, /UDQS and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). In this datasheet, DQS represents UDQS and LDQS, /DQS represents /UDQS and /LDQS. RDQS, /RDQS (output pins) Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS. ODT (input pins) ODT (On Die Termination control) is a registered high signal that enables termination resistance internal to the DDR 2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for × 4, × 8 configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT. Any time the EMRS enables the ODT function; ODT may not be driven high until eight clocks after the EMRS has been enabled. VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDDL and VSSDL (power supply) VDDL and VSSDL are power supply pins for DLL circuits. VREF (Power supply) SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ |
Similar Part No. - EDE1116ACSE-8E-E |
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Similar Description - EDE1116ACSE-8E-E |
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