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EDE1116ACSE-8E-E Datasheet(PDF) 14 Page - Elpida Memory

Part # EDE1116ACSE-8E-E
Description  1G bits DDR2 SDRAM
Download  82 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDE1116ACSE-8E-E Datasheet(HTML) 14 Page - Elpida Memory

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EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
Data Sheet E0975E50 (Ver.5.0)
14
AC Characteristics (TC = 0
°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-800, 667]
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-6E
Speed bin
DDR2-800 (5-5-5)
DDR2-667 (5-5-5)
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Active to read or write command delay
tRCD
12.5
15
ns
Precharge command period
tRP
12.5
15
ns
Active to active/auto-refresh command time tRC
57.5
60
ns
DQ output access time from CK, /CK
tAC
−400
+400
−450
+450
ps
10
DQS output access time from CK, /CK
tDQSCK
−350
+350
−400
+400
ps
10
CK high-level width
tCH (avg)
0.48
0.52
0.48
0.52
tCK (avg) 13
CK low-level width
tCL(avg)
0.48
0.52
0.48
0.52
tCK (avg) 13
CK half period
tHP
Min. (tCL(abs),
tCH(abs))
Min.(tCL(abs),
tCH(abs))
ps
6, 13
Clock cycle time
(CL = 6)
tCK (avg)
2500
8000
3000
8000
ps
13
(CL = 5)
tCK (avg)
2500
8000
3000
8000
ps
13
(CL = 4)
tCK (avg)
3750
8000
3750
8000
ps
13
(CL = 3)
tCK (avg)
5000
8000
5000
8000
ps
13
DQ and DM input hold time
tDH (base) 125
175
ps
5
DQ and DM input setup time
tDS (base) 50
100
ps
4
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK (avg)
DQ and DM input pulse width for each input tDIPW
0.35
0.35
tCK (avg)
Data-out high-impedance time from CK,/CK tHZ
tAC max.
tAC max. ps
10
DQS, /DQS low-impedance time from
CK,/CK
tLZ (DQS) tAC min.
tAC max.
tAC min.
tAC max. ps
10
DQ low-impedance time from CK,/CK
tLZ (DQ)
2
× tAC min.
tAC max.
2
× tAC min.
tAC max. ps
10
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
200
240
ps
DQ hold skew factor
tQHS
300
340
ps
7
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
tHP – tQHS
ps
8
DQS latching rising transitions to associated
clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK (avg)
DQS input high pulse width
tDQSH
0.35
0.35
tCK (avg)
DQS input low pulse width
tDQSL
0.35
0.35
tCK (avg)
DQS falling edge to CK setup time
tDSS
0.2
0.2
tCK (avg)
DQS falling edge hold time from CK
tDSH
0.2
0.2
tCK (avg)
Mode register set command cycle time
tMRD
2
2
nCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK (avg)
Write preamble
tWPRE
0.35
0.35
tCK (avg)
Address and control input hold time
tIH (base) 250
275
ps
5
Address and control input setup time
tIS (base) 175
200
ps
4
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK (avg) 11
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK (avg) 12
Active to precharge command
tRAS
45
70000
45
70000
ns


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