 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EDE1116AEBG Datasheet(PDF) 15 Page - Elpida Memory |
|
||||||||||||||||||||||||||||||
EDE1116AEBG Datasheet(HTML) 15 Page - Elpida Memory |
|
|
15 / 78 page  EDE1108AEBG, EDE1116AEBG Preliminary Data Sheet E1228E20 (Ver. 2.0) 15 -8E -6E Speed bin DDR2-800 (5-5-5) DDR2-667 (5-5-5) Parameter Symbol min. max. min. max. Unit Notes Active to auto-precharge delay tRAP tRCD min. ⎯ tRCD min. ⎯ ns Active bank A to active bank B command period (EDE1108AE) tRRD 7.5 ⎯ 7.5 ⎯ ns (EDE1116AE) tRRD 10 ⎯ 10 ⎯ ns Four active window period (EDE1108AE) tFAW 35 ⎯ 37.5 ⎯ ns (EDE1116AE) tFAW 45 ⎯ 50 ⎯ ns /CAS to /CAS command delay tCCD 2 ⎯ 2 ⎯ nCK Write recovery time tWR 15 ⎯ 15 ⎯ ns Auto precharge write recovery + precharge time tDAL WR + RU (tRP/tCK(avg)) ⎯ WR + RU (tRP/tCK(avg)) ⎯ nCK 1, 9 Internal write to read command delay tWTR 7.5 ⎯ 7.5 ⎯ ns 14 Internal read to precharge command delay tRTP 7.5 ⎯ 7.5 ⎯ ns Exit self-refresh to a non-read command tXSNR tRFC + 10 ⎯ tRFC + 10 ⎯ ns Exit self-refresh to a read command tXSRD 200 ⎯ 200 ⎯ nCK Exit precharge power down to any non-read command tXP 2 ⎯ 2 ⎯ nCK Exit active power down to read command tXARD 2 ⎯ 2 ⎯ nCK 3 Exit active power down to read command (slow exit/low power mode) tXARDS 8 − AL ⎯ 7 − AL ⎯ nCK 2, 3 CKE minimum pulse width (high and low pulse width) tCKE 3 ⎯ 3 ⎯ nCK Output impedance test driver delay tOIT 0 12 0 12 ns MRS command to ODT update delay t MOD 0 12 0 12 ns Auto-refresh to active/auto-refresh command time tRFC 127.5 ⎯ 127.5 ⎯ ns Average periodic refresh interval (0 °C ≤ TC ≤ +85°C) tREFI ⎯ 7.8 ⎯ 7.8 μs (+85 °C < TC ≤ +95°C) tREFI ⎯ 3.9 ⎯ 3.9 μs Minimum time clocks remains ON after CKE asynchronously drops low tDELAY tIS + tCK(avg) + tIH ⎯ tIS + tCK(avg) + tIH ⎯ ns Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer. 2. AL: Additive Latency. 3. MRS A12 bit defines which active power down exit timing to be applied. 4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test. DQS /DQS tDS tDH tDS tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VIL (DC)(max.) VIL (AC)(max.) VSS VREF CK /CK tIS tIH tIS tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VIL (DC)(max.) VIL (AC)(max.) VSS VREF Input Waveform Timing 1 (tDS, tDH) Input Waveform Timing 2 (tIS, tIH) |
Similar Part No. - EDE1116AEBG |
|
Similar Description - EDE1116AEBG |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
