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EDE1116ACSE-LI Datasheet(PDF) 41 Page - Elpida Memory |
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EDE1116ACSE-LI Datasheet(HTML) 41 Page - Elpida Memory |
41 / 75 page EDE1116ACSE-LI Data Sheet E1103E20 (Ver. 2.0) 41 For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the Output Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS addressing mode (i.e. sequential or interleave). Command EMRS OCD adjust mode OCD calibration mode exit NOP DT0 tDS tDH DT1 DT2 DT3 NOP EMRS CK /CK WL tWR DQS, /DQS DQ_in Output Impedance Control Register Set Cycle Drive Mode Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance Measurement/Verify Cycle”. Command Enter drivemode OCD Calibration mode exit NOP CK /CK DQS, /DQS High-Z High-Z DQs high for drive (1) DQs low for drive (0) tOIT DQ EMRS EMRS tOIT DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0) Output Impedance Measurement/Verify Cycle |
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