MCP3008T datasheet(17/40 Pages) MICROCHIP | 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

Part No.	MCP3008T

Description	2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

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DS21295D-page 17

MCP3004/3008

4.0

DEVICE OPERATION

The MCP3004/3008 A/D converters employ a

conventional SAR architecture. With this architecture,

a sample is acquired on an internal sample/hold

capacitor for 1.5 clock cycles starting on the first rising

edge of the serial clock once CS has been pulled low.

Following this sample time, the device uses the

collected charge on the internal sample and hold

capacitor to produce a serial 10-bit digital output code.

Conversion rates of 100 ksps are possible on the

MCP3004/3008. See Section 6.2 “Maintaining Mini-

mum Clock Speed”

, “Maintaining Minimum Clock

Speed”, for information on minimum clock rates.

Communication with the device is accomplished using

a 4-wire SPI-compatible interface.

4.1

Analog Inputs

The MCP3004/3008 devices offer the choice of using

the analog input channels configured as single-ended

inputs or pseudo-differential pairs. The MCP3004 can

be configured to provide two pseudo-differential input

pairs or four single-ended inputs. The MCP3008 can be

configured to provide four pseudo-differential input

pairs or eight single-ended inputs. Configuration is

done as part of the serial command before each

conversion begins. When used in the pseudo-

differential mode, each channel pair (i.e., CH0 and

CH1, CH2 and CH3 etc.) are programmed as the IN+

and IN- inputs as part of the command string transmit-

ted to the device. The IN+ input can range from IN- to

(VREF + IN-). The IN- input is limited to ±100 mV from

the VSS rail. The IN- input can be used to cancel small

signal common-mode noise, which is present on both

the IN+ and IN- inputs.

When operating in the pseudo-differential mode, if the

voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is

equal to or greater than {[VREF + (IN-)] - 1 LSB}, then

the output code will be 3FFh. If the voltage level at IN-

is more than 1 LSB below VSS, the voltage level at the

IN+ input will have to go below VSS to see the 000h

output code. Conversely, if IN- is more than 1 LSB

above VSS, the 3FFh code will not be seen unless the

IN+ input level goes above VREF level.

For the A/D converter to meet specification, the charge

holding capacitor (CSAMPLE) must be given enough

time to acquire a 10-bit accurate voltage level during

the 1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

This diagram illustrates that the source impedance (RS)

adds to the internal sampling switch (RSS) impedance,

directly affecting the time that is required to charge the

capacitor (CSAMPLE). Consequently, larger source

impedances increase the offset, gain and integral

linearity errors of the conversion (see Figure 4-2).

4.2

Reference Input

For each device in the family, the reference input

(VREF) determines the analog input voltage range. As

the reference input is reduced, the LSB size is reduced

accordingly.

EQUATION 4-1:

LSB SIZE CALCULATION

The theoretical digital output code produced by the A/D

converter is a function of the analog input signal and

the reference input, as shown below.

EQUATION 4-2:

DIGITAL OUTPUT CODE

CALCULATION

When using an external voltage reference device, the

system

designer

should

always

refer

to

the

manufacturer’s recommendations for circuit layout.

Any instability in the operation of the reference device

will have a direct effect on the operation of the A/D

converter.

LSB Size

V

REF

1024

-------------

=

Digital Output Code

1024

V

IN

×

V

REF

---------------------------

=

Where:

VIN

=

analog input voltage

VREF

=

analog input voltage

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