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STM32F103ZEY7XXX Datasheet(PDF) 71 Page - STMicroelectronics

Part # STM32F103ZEY7XXX
Description  High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103ZEY7XXX Datasheet(HTML) 71 Page - STMicroelectronics

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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Doc ID 14611 Rev 7
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Figure 31.
Synchronous non-multiplexed PSRAM write timings
Table 38.
Synchronous non-multiplexed PSRAM write timings(1)(2)
1.
CL = 15 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
27.7
ns
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
2
ns
td(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
THCLK + 2
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
4
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
5
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
0
ns
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
TCK + 2
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
1
ns
td(CLKH-NWEH)
FSMC_CLK high to FSMC_NWE high
THCLK + 1
ns
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
6
ns
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 1
BUSTURN = 0
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-AV)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14993e
FSMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-Data)
FSMC_NBL
td(CLKL-NBLH)


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