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DSP56001FC27 Datasheet(PDF) 3 Page - Motorola, Inc |
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DSP56001FC27 Datasheet(HTML) 3 Page - Motorola, Inc |
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3 / 64 page  3 DSP56001 MOTOROLA SIGNAL DESCRIPTION The DSP56001 is available in 132 pin surface mount (CQFP and PQFP) or an 88-pin pin-grid array packaging. Its input and output sig- nals are organized into seven functional groups which are listed below and shown in Figure 1. Port A Address and Data Buses Port A Bus Control Interrupt and Mode Control Power and Clock Host Interface or Port B I/O Serial Communications Interface or Port C I/O Synchronous Serial Interface or Port C I/O PORT A ADDRESS AND DATA BUS Address Bus (A0-A15) These three-state output pins specify the address for external program and data memory accesses. To minimize power dissipation, A0-A15 do not change state when external memory spaces are not being ac- cessed. Data Bus (D0-D23) These pins provide the bidirectional data bus for external program and data memory accesses. D0-D23 are in the high-impedance state when the bus grant signal is asserted. PORT A BUS CONTROL Program Memory Select (PS) This three-state output is asserted only when external program mem- ory is referenced. This pin is three-stated during RESET. Data Memory Select (DS) This three-state output is asserted only when external data memory is referenced. This pin is three-stated during RESET. X/Y Select (X/Y) This three-state output selects which external data memory space (X or Y) is referenced by data memory select (DS). This pin is three-stat- ed during RESET. Read Enable (RD) This three-state output is asserted to read external memory on the data bus D0-D23. This pin is three-stated during RESET. Write Enable (WR) This three-state output is asserted to write external memory on the data bus D0-D23. This pin is three-stated during RESET. Bus Request (BR/WT) The bus request input BR allows another device such as a processor or DMA controller to become the master of external data bus D0-D23 and external address bus A0-A15. When operating mode register (OMR) bit 7 is clear and BR is asserted, the DSP56001 will always re- lease the external data bus D0-D23, address bus A0-A15, and bus control pins PS, DS, X/Y, RD, and WR (i. e., Port A), by placing these pins in the high-impedance state after execution of the current instruc- tion has been completed. The BR pin should be pulled up when not in use. If OMR bit 7 is set, this pin is an input that allows an external device to force wait states during an external Port A operation for as long as WT is asserted. Bus Grant (BG/BS) If OMR bit 7 is clear, this output is asserted to acknowledge an external bus request after Port A has been released. If OMR bit 7 is set, this pin is bus strobe and is asserted when the DSP accesses Port A. This pin is three-stated during RESET. INTERRUPT AND MODE CONTROL Mode Select A/External Interrupt Request A (MODA/IRQA), Mode Select B/External Interrupt Request B (MODB/IRQB) These two inputs have dual functions: 1) to select the initial chip oper- ating mode and 2) to receive an interrupt request from an external source. MODA and MODB are read and internally latched in the DSP when the processor exits the RESET state. Therefore these two pins should be forced into the proper state during reset. After leaving the RESET state, the MODA and MODB pins automatically change to ex- ternal interrupt requests IRQA and IRQB. After leaving the reset state the chip operating mode can be changed by software. IRQA and IRQB may be programmed to be level sensitive or negative edge triggered. When edge triggered, triggering occurs at a voltage level and is not di- rectly related to the fall time of the interrupt signal, however, the prob- ability of noise on IRQA or IRQB generating multiple interrupts increas- es with increasing fall time of the interrupt signal. These pins are inputs during RESET. Reset (RESET) This Schmitt trigger input pin is used to reset the DSP56001. When RESET is asserted, the DSP56001 is initialized and placed in the reset state. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA and MODB pins. When coming out of reset, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal; however, the probability of noise on RESET generating multiple resets increases with increasing rise time of the reset signal. POWER AND CLOCK Power (Vcc), Ground (GND) There are five sets of power and ground pins used for the four groups of logic on the chip, two pairs for internal logic, one power and two ground for Port A address and control pins, one power and two ground for Port A data pins, and one pair for peripherals. Refer to the pin as- signments in the LAYOUT PRACTICES section. PORT A PORT B PORT C HOST CONTROL RXD TXD SCLK SC0 SC1 SCK SRD STD A0-A15 D0-D23 PS DS RD WR X/Y BR/WT BG/BS HOST DATA BUS BUS CONTROL ADDRESS DATA DSP56001 Figure 2. Functional Signal Groups SCI SSI |
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