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STM32W108CBU62 Datasheet(PDF) 7 Page - STMicroelectronics |
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STM32W108CBU62 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 179 page STM32W108CB, STM32W108HB Contents Doc ID 16252 Rev 2 7/179 9.1.3 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.1.4 Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.1.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.1.6 ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.1.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.1.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.3 Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 138 9.3.1 ADC configuration register (ADC_CFG) . . . . . . . . . . . . . . . . . . . . . . . 138 9.3.2 ADC offset register (ADC_OFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.3.3 ADC gain register (ADC_GAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.3.4 ADC DMA configuration register (ADC_DMACFG) . . . . . . . . . . . . . . . 139 9.3.5 ADC DMA status register (ADC_DMASTAT) . . . . . . . . . . . . . . . . . . . . 140 9.3.6 ADC DMA begin address register (ADC_DMABEG) . . . . . . . . . . . . . . 140 9.3.7 ADC DMA buffer size register (ADC_DMASIZE) . . . . . . . . . . . . . . . . . 141 9.3.8 ADC DMA current address register (ADC_DMACUR) . . . . . . . . . . . . . 141 9.3.9 ADC DMA count register (ADC_DMACNT) . . . . . . . . . . . . . . . . . . . . . 141 9.3.10 ADC interrupt flag register (INT_ADCFLAG) . . . . . . . . . . . . . . . . . . . . 142 9.3.11 ADC interrupt configuration register (INT_ADCCFG) . . . . . . . . . . . . . 142 10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 143 10.1.1 Non-maskable interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.1.2 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.2 Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.3 Nested vectored interrupt controller (NVIC) interrupts . . . . . . . . . . . . . . 149 10.3.1 Top-level set interrupts configuration register (INT_CFGSET) . . . . . . 149 10.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) . . . . . 149 10.3.3 Top-level set interrupts pending register (INT_PENDSET) . . . . . . . . . 150 10.3.4 Top-level clear interrupts pending register (INT_PENDCLR) . . . . . . . . 151 10.3.5 Top-level active interrupts register (INT_ACTIVE) . . . . . . . . . . . . . . . . 152 10.3.6 Top-level missed interrupts register (INT_MISS) . . . . . . . . . . . . . . . . . 153 10.3.7 Auxiliary fault status register (SCS_AFSR) . . . . . . . . . . . . . . . . . . . . . 153 11 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 |
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