STM32F101CB datasheet(55/81 Pages) STMICROELECTRONICS

Part #	STM32F101CB

Description	Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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STM32F101x8, STM32F101xB

Electrical characteristics

Doc ID 13586 Rev 12

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Figure 22.

I/O AC characteristics definition

5.3.13

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 33).

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 8.

Figure 23.

Recommended NRST pin

protection

1.

The reset network protects the device against parasitic resets.

2.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 36. Otherwise the reset will not be taken into account by the device.

ai14131

10%

90%

50%

tr(IO)out

OUTPUT

EXT ERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)

10%

50%

90%

when loaded by 50pF

T

tr(IO)out

Table 36.

NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST)

(1)

1.

Guaranteed by design, not tested in production.

NRST Input low level voltage

–0.5

0.8

V

VIH(NRST)

(1)

NRST Input high level voltage

2

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

mV

RPU

Weak pull-up equivalent resistor(2)

2.

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum

(~10% order)

.

VIN VSS

30

40

50

k



VF(NRST)

(1)

NRST Input filtered pulse

100

ns

VNF(NRST)

(1)

NRST Input not filtered pulse

300

ns

ai14132c

STM32F10xxx

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 µF

External

reset circuit(1)

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