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MPC2F35E2 Datasheet(PDF) 9 Page - Megawin Technology Co., Ltd |
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MPC2F35E2 Datasheet(HTML) 9 Page - Megawin Technology Co., Ltd |
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9 / 46 page  MEGAWIN MPC2F35_USB Data Sheet 9 Interrupt Registers IRQ enable flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C1H IRQ_EN - - INT1 INT0 P3 TM0 USB - √ √ Program can enable (setting to “1”) or disable (clearing to “0”) the ability of triggering IRQ through this register. USB: USB finishes Rx or Tx data TM0: Timer0 underflow P3: Falling edge trigger signal occurs at port 3 input mode INT0, INT1: Falling edge trigger signal occurs at P0.4 and P0.5 input mode IRQ status flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C2H IRQ_ST - - INT1 INT0 P3 TM0 USB - √ - When IRQ occurs, program can read this register to know which source triggering IRQ. IRQ clear flag Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00C3H IRQ_CLR - - INT1 INT0 P3 TM0 USB - - √ Program can clear the interrupt event by writing ‘1’ into the corresponding bit. Watchdog Timer (WDT) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 00DEH WDT_ST RSTS - - - Bit 3Bit 2Bit 1 Bit 0 √ - 00DFH WDT_CLR CLR - - - - - - - - √ Bit 3 ~ Bit 0: Contents of WDT RSTS: WDT reset status, set by the hardware when WDT overflows, and clear by the firmware or the hardware reset CLR: RSTS clear and WDT reset control bit, the program can clear the RSTS bit and reset WDT by writing “1” into the CLR bit The watchdog timer (WDT) is organized as a 4-bit counter, which is designed to prevent the program from unknown errors. If the WDT overflows, the WDT reset function will be performed. RSTS (Bit 7 of WDT_ST) is set by hardware when the WDT overflows. It also can be cleared by hardware reset or writing 1 to bit 7 of WDT_CLR. The interval of WDT to cause reset is around 0.7s at 6MHz external oscillator. Programming one into the bit 7 of WDT_CLR register can reset the contents of the WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The organization of the watchdog timer is shown as below |
Similar Part No. - MPC2F35E2 |
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Similar Description - MPC2F35E2 |
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