CS5509

DS125F3

7

Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high

proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than

17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial

port shifting mechanism before falling edges can be recognized.

18. If CS is returned high before all data bits are output, the SDATA output will complete the current data

bit and then go to high impedance.

Parameter

Symbol

Min

Typ

Max

Unit

Serial Clock

0-

2.5

MHz

Serial Clock

Pulse Width High

Pulse Width Low

200

200

-

-

-

-

ns

ns

Access Time

CS Low to data valid (Note 16)

-60

200

ns

Maximum Delay Time

(Note 17)

SCLK falling to new SDATA bit

-150

310

ns

Output Float Delay

CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

-

-

60

160

150

300

ns

ns

Parameter

Symbol

Min

Typ

Max

Unit

Serial Clock

0

-

1.25

MHz

Serial Clock

Pulse Width High

Pulse Width Low

200

200

-

-

-

-

ns

ns

Access Time

CS Low to data valid (Note 16)

-100

200

ns

Maximum Delay Time

(Note 17)

SCLK falling to new SDATA bit

-400

600

ns

Output Float Delay

CS High to output Hi-Z (Note 18)

SCLK falling to Hi-Z

-

-

70

320

150

500

ns

ns