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XR21V1412 Datasheet(PDF) 7 Page - Exar Corporation |
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XR21V1412 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 24 page XR21V1412 7 REV. 1.0.0 2-CH FULL-SPEED USB UART 1.2.1 EEPROM Contents The I2C address should be 0xA0. An EEPROM can be used to override default Vendor IDs and Device IDs, as well as other attributes and maximum power consumption. The EEPROM must contain 8 bytes of data as specified in Table 2 TABLE 2: EEPROM CONTENTS ADDRESS CONTENTS 0 Vendor ID (LSB) 1 Vendor ID (MSB) 2 Product ID (LSB) 3 Product ID (MSB) 4 Device Attributes 5 Device Maximum Power 6 Reserved 7 Signature of 0x58 (’X’). If the signature is not correct, the contents of the EEPROM are ignored. These values are uploaded from the EEPROM to the corresponding USB Standard Device Descriptor or Standard Configuration Descriptor. For details of the USB Descriptors, refer to the USB 2.0 specifications. 1.2.1.1 Vendor ID The Vendor ID value replaces the idVendor field in the USB Standard Device Descriptor. 1.2.1.2 Product ID The Product ID value replaces the idProduct field in the USB Standard Device Descriptor. 1.2.1.3 Device Attributes The Device Attributes value replaces the bmAttributes field in the USB Standard Configuration Descriptor. 1.2.1.4 Device Maximum Power The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration Descriptor. 1.3 UART Manager The UART Manager enables/disables each UART including the TX and RX FIFOs for each UART. The UART Manager is located in a separate register block from the 2 UART channels. 1.4 UART There are 2 enhanced UART channels in the V1412. Each UART channel is independent, therefore, they will need to be initialized and configured independently. Each UART can be configured via USB control transfers from the USB host. 1.4.1 Transmitter The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at the data rate defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stop- bit(s). The transmitter can be configured for 7 or 8 data bits with parity or 9 data bits with no parity. EEPROM |
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