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XR20V2172IL64 Datasheet(PDF) 6 Page - Exar Corporation |
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XR20V2172IL64 Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 53 page  XR20V2172 6 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. 1.0.1 1.0 PRODUCT DESCRIPTION The XR20V2172 (V2172) integrates a selectable I2C/SPI bus interface with an enhanced two channel Universal Asynchronous Receiver and Transmitter (UART) and an RS-232 Transceiver. The configuration register set is 16550 UART compatible for control, status and data transfer. Additionally, each channel of the V2172 has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/ Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, programmable fractional baud rate generator with a prescaler of divide by 1 or 4, data rate up to 1 Mbps, while meeting all EIA RS-232F specifications. Additionally, the V2172 includes the ACP pin with which the user can shut down the charge pump for the RS-232 drivers when the V2172 is already in sleep mode. The XR20V2172 is a 3.3 to 5.5V device. The V2172 is fabricated with an advanced CMOS process. Enhanced Features The V2172 UART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes in the industry standard 16C550. The V2172 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. Increased performance is realized in the V2172 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the V2172, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption. Finally, since the V2172 includes an RS-232 transceiver and a full-modem interface, it can be connected to an RS-232 serial cable directly. Data Rate The V2172 is capable of operation up to 1 Mbps data rate using the 16X, 8X or 4X internal sampling clock rate. The UART section can operate at much higher speeds, but the speed of the RS-232 transceiver is limited to 1Mbps beyond which the V2172 cannot comply with the EIA/TIA-232 electrical characteristics. The device can operate either with a crystal on pins XTAL1 and XTAL2, or external clock source on XTAL1 pin. RS-232 Interface The V2172 includes RS-232 drivers/receivers for the modem interface. This feature eliminates the need for an external RS-232 transceiver. The charge pump provides output voltages of +5V and -5V for its drivers over the 3.3V to 3.63V power supply voltage range. The serial outputs TXD swing between -5V (inactive) and +5V (active) RS-232 voltage levels. The serial inputs RXD are RS-232 receivers and can take any voltage swing from -15V to +15V. The receivers are always active, even in Sleep mode. The RS-232 drivers guarantee a data rate of 1 Mbps even when fully loaded with 3Kohm in parallel with 1000pF load. All RS-232 drivers and receivers are protected to ±15kV using the Human Body Model ground combination, ±8kV using IEC 61000-4-2 Contact Discharge, and ±15kV using IEC 61000-4-2 Air-Gap Discharge. For more information, send an e-mail to uarttechsupport@exar.com. |
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