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XR20V2172 Datasheet(PDF) 8 Page - Exar Corporation |
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XR20V2172 Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 53 page  XR20V2172 8 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. 1.0.1 2.2 I2C-bus Addressing There could be many devices on the I2C-bus. To distinguish itself from the other devices on the I2C-bus, there are eight possible slave addresses that can be selected for the V2172 using the A1 and A0 address lines. Table 1 below shows the different addresses that can be selected. Note that there are two different ways to select each I2C address. An I2C sub-address is sent by the I2C master following the slave address. The sub-address contains the UART register address being accessed. A read or write transaction is determined by bit-0 of the slave address. If bit-0 is’0’, then it is a write transaction. If bit-0 is ’1’, then it is a read transaction. Table 2 below lists the functions of the bits in the I2C sub-address. After the last read or write transaction, the I2C-bus master will set the SCL signal back to its idle state (HIGH). TABLE 1: XR20V2172 I2C ADDRESS MAP A1 A0 I2C ADDRESS VCC VCC 0x60 (0110 000X) VCC GND 0x62 (0110 001X) VCC SCL 0x64 (0110 010X) VCC SDA 0x66 (0110 011X) GND VCC 0x68 (0110 100X) GND GND 0x6A (0110 101X) GND SCL 0x6C (0110 110X) GND SDA 0x6E (0110 111X) SCL VCC 0x60 (0110 000X) SCL GND 0x62 (0110 001X) SCL SCL 0x64 (0110 010X) SCL SDA 0x66 (0110 011X) SDA VCC 0x68 (0110 100X) SDA GND 0x6A (0110 101X) SDA SCL 0x6C (0110 110X) SDA SDA 0x6E (0110 111X) TABLE 2: I2C SUB-ADDRESS BIT FUNCTION 7 Reserved 6:3 UART Internal Register Address A3:A0 2:1 UART Channel Select ’00’ = UART Channel A ’01’ = UART Channel B 0 Reserved |
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