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XR18W750IL48 Datasheet(PDF) 10 Page - Exar Corporation |
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XR18W750IL48 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 44 page XR18W750 10 WIRELESS UART CONTROLLER REV. 1.0.0 3.2 Parallel Mode (CPU) Interface In the parallel mode, the CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The XR18W750 data interface supports both the Intel and Motorola compatible types of CPUs and is compatible to the industry standard 16C550 UART. Each bus cycle is asynchronous using CS#, IOR# and IOW#, or CS# and R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. XR18W750 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS (PARALLEL MODE) 8051 Microprocessor S/P# A2:A0 D7:D0 CS# IOW# IOR# INT A2:A0 D7:D0 CS# IOW# IOR# RESET A2:A0 D7:D0 UART_CS# IOW# IOR# RESET TXRDY# RXRDY# TXRDY# RXRDY# 16/68# VCC UART GND INT UART_INT Intel Data Bus Interconnections UART RX TX CTS# RTS# TX RX RTS# CTS# 8051 Microprocessor S/P# A2:A0 D7:D0 CS# IOW# IOR# INT A2:A0 D7:D0 CS# IOW# IOR# RESET A2:A0 D7:D0 UART_CS# R/W# VCC RESET# TXRDY# RXRDY# TXRDY# RXRDY# 16/68# GND UART GND INT UART_IRQ# VCC Motorola Data Bus Interconnections UART RX TX CTS# RTS# TX RX RTS# CTS# |
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