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XR17V352 Datasheet(PDF) 26 Page - Exar Corporation |
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XR17V352 Datasheet(HTML) 26 Page - Exar Corporation |
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26 / 64 page  XR17V352 PRELIMINARY 26 HIGH PERFORMANCE DUAL PCI EXPRESS UART REV. P1.0.1 MPIOINT [15:0] (default 0x00) The MPIOINT register enables the multipurpose input pin interrupt. If an MPIO pin is selected by MPIOSEL as an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin MPIO0 for interrupt, and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active LOW or active HIGH. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it. MPIO6 MPIO7 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOINT Register Multipurpose Input/Output Interrupt Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIOLVL [15:0] (default 0x00) The MPIOLVL register controls the output pins and provides the input level status for the input pins. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets the output to LOW and a logic 1 sets the output pin to HIGH. The MPIO interrupt will clear upon reading this register. MPIO6 MPIO7 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOLVL Register Multipurpose Output Level Control Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO3T [15:0] (default 0x00) The MPIO outputs can be tri-stated by the MPIO3T register. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a logic 1 sets the output pin to tri-state. MPIO6 MPIO7 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIO3T Register Multipurpose Output 3-state Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIOINV [15:0] (default 0x00) The MPIO inputs can be inverted by the MPIOINV register. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic level. MPIO6 MPIO7 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOINV Register Multipurpose Input Signal Inversion Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 |
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