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XR17V352 Datasheet(PDF) 11 Page - Exar Corporation |
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XR17V352 Datasheet(HTML) 11 Page - Exar Corporation |
11 / 64 page PRELIMINARY XR17V352 11 REV. P1.0.1 HIGH PERFORMANCE DUAL PCI EXPRESS UART 0x80 31:16 RO PCI Express 2.0 capable endpoint, Interrupt Message Number 1 0x0202 15:8 RO Next Capability Pointer 0x00 7:0 RO PCI Express Capability ID 0x10 0x84 31:16 RO Not implemented or not applicable (return zeros) 0x0000 15:8 RO Role-Based Error Reporting 0x80 7:0 RO 256 bytes max payload size 0x01 0x88 31:16 RW Not implemented or not applicable (return zeros) 0x0000 15:8 RW 512 bytes max read request, Enable No Snoop 0x28 7:0 RW 256 bytes max TLP payload size 0x10 0x8C 31:24 RO Port Number 0x01 23:22 RO Not implemented or not applicable (return zeros) 00b 21:18 RO Not implemented or not applicable (return zeros) 0000b 17:15 RO L1 Exit Latency < 1 us 000b 14:12 RO L0s Exit Latency < 64 ns 000b 11:10 RO Active State Power Management (ASPM) Support L0s and L1 Supported 11b 9:4 RO x1 max Link Width 000001b 3:0 RO 2.5GT/s Link speed supported 0001b 0x90 31:21 RO Not implemented or not applicable (return zeros) 00000000000b 20 RO Data Link Layer Active Reporting capable 1b 19 RO Surprise Down Error Reporting not supported 0b 18 RO Reference clock must not be removed. 0b 17:15 RO L1 Exit Latency - 2 us to less than 4 us 010b 14:10 RO Not implemented or not applicable (return zeros) 00000b 9:4 RO x1 negotiated Link Width 000001b 3:0 RO Current Link Speed is 2.5GT/s 0001b 0x94 31:0 RO PCIe Capability Offset 0x14 - Slot Capabilities Register 0x00040000 0x98-0xAF 31:0 RO Not implemented or not applicable (return zeros) 0x00000000 0xB0 31:0 RO PCIe Capability Offset 0x30 - Link Status2/Control2 0x00010001 0xB4-0xFF 31:0 RO Not implemented or not applicable (return zeros) 0x00000000 0x100 31:0 RO VC Resource Capability Register 0x00010002 TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ADDRESS OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY) |
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