Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com

Page 5 of 8

Table 7. Pin Functions

Pin #

Symbol

I/O

Level

Function

1

SEL0

I

LVCMOS

Frequency Select - see table 3

2

SEL1

I

LVCOMS

Frequency Select – see table 3

3

GND

GND

Supply

Case and Electrical Ground

4

Not present

5

VMON

O

VCXO Control Voltage Monitor

Under locked conditions VMON should be > 0.3V and <3.0V. The input fre-

quency may be out of range if the voltage exceeds these levels

6

OD

I

LVCMOS

Output Disable

Disabled = Logic “1”

Enabled = Logic “0” or no connect

7

LD

O

LVCMOS

Lock Detect

Locked = Logic “1”

Loss of Lock = Logic “0”

8

FOUT1

O

LCPECL

Frequency Output – Primary

9

CFOUT1

O

LVPECL

Complimentary Frequency Output - Primary

10

FOUT2

O

LVPECL

Divided-Down VCSO/VCXO Output, or Disabled

11

CFOUT2

O

LVPECL

Complimentary Divided-Down VCSO/VCXO Output, or Disabled

12

GND

GND

Supply

Case and Electrical Ground

13

FIN

I

LVCMOS or

LVPECL

Input Frequency – AC Coupled

14

VCC

VCC

Supply

Power Supply Voltage (3.3 V ±5%)

LVCMOS input signal levels are valid for input frequencies < 100 MHz.

Table 8. Control Logic (LVCMOS)

SEL 0

SEL 1

CLock Input

0

0

FIN

1

0

1

FIN

2

1

0

FIN

3

1

1

FIN

4

Pin Configuration

Rev: 8/13/2009

Figure 6. Pin Configuration