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FX-702-EDT-SMM Datasheet(PDF) 5 Page - Vectron International, Inc |
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FX-702-EDT-SMM Datasheet(HTML) 5 Page - Vectron International, Inc |
5 / 7 page 5 5 of 7 Table 7. Pin Functions Pad # Symbol I/O Level Function 1 BRCLK I NC or LVPE- CL, LVDS NC or For External divider application = PD Feedback Frequency 2LD1 O CMOS Lock Detect Logic 0 = FX Locked Logic 1 - No Input Output transitioning = Out of Lock 3 GND GND Supply Case and electrical ground 4 MODE2 I CMOS FX Operating Mode Logic 0 = Standard PLL (Normal Setting) Logic 1 = FIN coupled to FOUT 5 GND GND Supply Case and electrical ground 6 LFN Analog Loop Filter Node 7 CLFN Analog Complementary Loop Filter Node 8 FOUT O LVPECL or LVDS Frequency Output 9 CFOUT O LVPECL or LVDS Complementary Frequency Output 10 VCC I Supply Power Supply Voltage (+3.3V ±5%) 11 CFIN I LVPECL Complemetary Input Frequency For CMOS inouts, AC-couple unused inputto ground or negative supply 12 FIN I CMOS or LVPECL Input Frequency 13 GND GND Supply Case and electrical ground 14 CBRCLK I NC or LVPE- CL, LVDS NC or For External divider applications = Comp. PD Feedback Frequency 1. It is recommended that a buffer driver is used for best noise isolation. 2. Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation. 3. BRCLK and CBRCLK should be left floating if not used. 4. FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs. Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Rev: 03Apr2009 Figure 5. Outline Diagram FX702 YWW CCC-CCCC ▲ XX-XX |
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