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XRT75R12IB Datasheet(PDF) 76 Page - Exar Corporation |
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XRT75R12IB Datasheet(HTML) 76 Page - Exar Corporation |
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76 / 90 page  XRT75R12 73 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 TABLE 35: XRT75R12 REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_n) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Reserved Internal Transmit Drive Monitor Insert PRBS Error Reserved TAOS TxCLKINV TxLEV R/W R/W R/W R/W R/W TABLE 36: TRANSMIT CONTROL REGISTER - CHANNEL n ADDRESS LOCATION = 0XM4 (n = [0:11] & M= 0-5 & 8-D) BIT NUMBER NAME TYPE DESCRIPTION 7 - 6 Reserved 5 Internal Transmit Drive Monitor Enable R/W Internal Transmit Drive Monitor Enable - Channel_n: This READ/WRITE bit-field is used to configure the Transmit Section of Channel_n to either internally or externally monitor the TTIP_n and TRING_n output pins for bipolar pulses, in order to determine whether to declare the Transmit DMO Alarm condition. If the user configures the Transmit Section to externally monitor the TTIP_n and TRING_n output pins (for bipolar pulses) then the user must connect the MTIP_n and MRING_n input pins to their corresponding TTIP_n and TRING_n output pins (via a 270 ohm series resistor). If the user configures the Transmit Section to internally monitor the TTIP_n and TRING_n output pins (for bipolar pulses), the user does NOT need to conect the MTIP_n and MRING_n input pins. This monitoring will be per- formed internally at the TTIP_n and TRING_n pads. 0 - Configures the Transmit Drive Monitor to externally monitor the TTIP_n and TRING_n output pins for bipolar pulses. 1 - Configures the Transmit Drive Monitor to internally monitor the TTIP_n and TRING_n output pins for bipolar pulses. 4 Insert PRBS Error R/W Insert PRBS Error - Channel_n: A "0 to 1" transition within this bit-field causes the PRBS Generator (within the Transmit Section of Channel_n) to generate a single bit error within the outbound PRBS pattern-stream. NOTES: 1. This bit-field is only active if the PRBS Generator and Receiver have been enabled within the corresponding Channel. 2. After writing the "1" into this register, the user must execute a write operation to clear this particular register bit to "0" in order to facilitate the next "0 to 1" transition in this bit-field. 3 Reserved |
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Similar Description - XRT75R12IB |
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