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SMS24 Datasheet(PDF) 8 Page - Summit Microelectronics, Inc. |
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SMS24 Datasheet(HTML) 8 Page - Summit Microelectronics, Inc. |
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8 / 18 page  8 SMS24 2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. MEMORY OPERATION The SMS24 memory is configured as a 2K x 8 array. Data is received and transmitted via an industry standard two- wire interface. The bus was designed for two-way, two- line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located some- where on the bus Input Data Protocol Configuring and programming the SMS24 is done using the 2-wire serial interface. The device type address for this operation is 1001BIN. The protocol defines any device that sends data onto the bus as a “transmitter” and any device that receives data as a “re ceiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases the SMS24 will be a “slave” device, since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time because changes on the data line while SCL is high will be interpreted as a start or a stop condition. Table 3. Programming Register 1 B S M 7 65 4 3 2 1 B S L 0 x K C O LV Od d AT D2 D W1 D W0 D W s d n o c e S t u o e m i T g o d h c t a W s t i B t u o e m i T g o d h c t a W e d o M e l d I r o F F O à 00x s 4 . 0 à 01 1 s 8 . 0 à 10 0 s 6 . 1 à 10 1 s 2 . 3 à 11 0 s 4 . 6 à 111 x x x 0 D e c i v e T 0 1 0 1 s s e r d d A e p y 1 D e c i v e T 1 1 0 1 s s e r d d A e p y 0o t s d n o p s e R d d A s a i B n i P s s e r x 1s e r o n g I d d A s a i B n i P s s e r 0 V E S N E S ) V 5 2 . 1 ( d l o h s e r h T > s r e g g i r T x 1 V E S N E S ) V 5 2 . 1 ( d l o h s e r h T < s r e g g i r T 0s r e t s i g e R R P n e p O g n i t i r W r o f x 1g n i t i r W s r e t s i g e R R P k c o L t u o 2048 Table03 2.0 START and STOP Conditions When both the data and clock lines are high, the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high is defined as the “START” condition. A low-to-high transition on the data line while the clock is high is defined as the “STOP” condition. Figure 1. START and STOP Conditions Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmit- ting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to ACKnowledge that it received the eight bits of data. 2046 Fig01 2.0 SCL SDA In START Condition STOP Condition |
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