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XR16M781IL24 Datasheet(PDF) 6 Page - Exar Corporation |
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XR16M781IL24 Datasheet(HTML) 6 Page - Exar Corporation |
6 / 52 page XR16M781 6 1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE REV. 1.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is a VLIO bus interface. The VLIO bus interface is an 8-bit multiplexed address/data bus interface. Each bus cycle is asynchronous using CS#, LLA# and IOR# or IOW# inputs. A typical data bus interconnection for the VLIO bus interface is shown in Figure 3. FIGURE 3. XR16M781 TYPICAL VLIO DATA BUS INTERCONNECTIONS VCC VCC UART_CS# UART_IOR# UART_IOW# CS# IOR# IOW# UART_INT INT GND UART_RESET# RESET# RI# CD# DSR# CTS# RTS# DTR# RX TX PWRSAVE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Serial Transceivers of RS-232 RS-485 RS-422 Or Infrared POWERSAVE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 |
Similar Part No. - XR16M781IL24 |
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Similar Description - XR16M781IL24 |
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