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XR16M752IL32 Datasheet(PDF) 10 Page - Exar Corporation |
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XR16M752IL32 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 54 page XR16M752/XR68M752 10 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO REV. 1.1.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The XR16M752 data interface supports the Intel compatible types of CPUs while the XR68M752 supports both the Intel and Motorola compatible data interfaces. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share the same data bus for host operations. The data bus interconnections are shown in Figure 4. FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS VCC VCC OP2A# DSRA# CTSA# RTSA# DTRA# RXA TXA RIA# CDA# OP2B# DSRB# CTSB# RTSB# DTRB# RXB TXB RIB# CDB# GND A0 A1 A2 UART_CSA# UART_CSB# IOR# IOW # D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CSA# CSB# D0 D1 D2 D3 D4 D5 D6 D7 IOR # IOW # UART Channel A UART Channel B UART_INTB UART_INTA INTB INTA RXRDYA# TXRDYA# RXRDYA# TXRDYA# RXRDYB# TXRDYB# RXRDYB# TXRDYB# UART_RESET RESET Serial Interface of RS-232, RS-422 or RS-485 Serial Interface of RS-232, RS-422 or RS-485 (no connect) (no connect) 2.25 to 3.6 Volt VCC VCC OP2A# DSRA# CTSA# RTSA# DTRA# RXA TXA RIA# CDA# OP2B# DSRB# CTSB# RTSB# DTRB# RXB TXB RIB# CDB# GND A0 A1 A2 UART_CS# A3 R/W # D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CSA# CSB# D0 D1 D2 D3 D4 D5 D6 D7 IOR # IOW # UART Channel A UART Channel B UART_IRQ# INTB INTA RXRDYA# TXRDYA# RXRDYA# TXRDYA# RXRDYB# TXRDYB# RXRDYB# TXRDYB# RESET# VCC UART_RESET# (no connect) (no connect) (no connect) VCC Intel Data Bus Interconnections Motorola Data Bus Interconnections Serial Interface of RS-232, RS-422 or RS-485 Serial Interface of RS-232, RS-422 or RS-485 |
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