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XR16M580IB25 Datasheet(PDF) 4 Page - Exar Corporation |
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XR16M580IB25 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 56 page XR16M580 4 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0 PIN DESCRIPTIONS Pin Description NAME 32-QFN PIN# 48-TQFP PIN# 25-BGA PIN# TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 17 18 19 26 27 28 A5 A4 B4 I Address lines [2:0]. These 3 address lines select the internal regis- ters in UART channel during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 5 4 3 1 32 31 30 29 4 3 2 47 46 45 44 43 C3 C2 E3 E1 D1 E2 D2 C1 I/O Data bus lines [7:0] (bidirectional). IOR# 14 19 B5 I When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge insti- gates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the ris- ing edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input should be connected to VCC. IOW# (R/W#) 12 16 C5 I When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. CS# 8 11 D4 I This input is chip select (active low) to enable the device. INT (IRQ#) 20 30 A3 O (OD) When 16/68# pin is at logic 1 for Intel bus interface, this output become the active high device interrupt output. The output state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the active low device interrupt output (open drain). An external pull-up resistor is required for proper operation. MODEM OR SERIAL I/O INTERFACE TX 7 8 D3 O UART Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected. |
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