SC63C0316

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

REV:1.0

2004.08.03

Http: www.silan.com.cn

Page 17 of 24

PHASE DETECTOR, CHARGE PUMP, AND UNLOCK DETECTOR

The phase comparator compares the phase difference between divided frequency (fN) output from the

programmable divider and the reference frequency (fr) output from the reference frequency generator.

The charge pump outputs the phase comparator's output from error output pins EO. The relation between the

error output pin output, divided frequency fN, and reference frequency fr is shown below:

When PLL operation is started by setting PLMOD register, PLL unlock flag (ULFG) in the PLL flag register

(PLLREG) has unlock state information between the reference frequency and divided frequency. The unlock

detector detects the unlock state of the PLL frequency synthesizer. The unlock flag in the PLLREG register is set

to "1" in unlock state. If ULFG = "0", the PLL lock state is selected.

PLLREG

ULFG

CEFG

IFCFG

0

ULFG is set continuously at a period of reference frequency f r by unlock detector. You must therefore read

ULFG flag in the PLLREG register at periods longer than 1/f r of the reference frequency. ULFG is reset when it

is read. PLLREG register can be read by 1-bit or 4-bit RAM control register instructions.

PLL operation is decided by CE (chip enable) pin state. The PLL frequency synthesizer is disabled and the

error output pin is set to floating state while the CE pin is low. When CE pin is high level, PLL is operating

normally.

The chip enable flag (CEFG) in the PLLREG register has information about CE pin state. When the CE pin

changes its low state to high, CEFG flag is set to logic one and CE reset operation occurs. When the CE pin

changes its high state to low, CEFG flag is set to logic zero and CE interrupt is generated.

INTERMEDIATE FREQUENCY COUNTER

The SC63C0316 uses an intermediate frequency counter (IFC) to count the frequency of the AM or FM signal

at FMIF or AMIF pin. The IFC block consists of a 1/2 divider, gate control circuit, IFC mode register (IFMOD) and

a 16-bit binary counter.

During gate time, the 16-bit IFC counts the input frequency at the FMIF or AMIF pins. The FMIF or AMIF pin

input signal for the 16-bit counter is selected by IFMOD register. The 16-bit binary counter (IFCNT1–IFCNT0) can

be read by 8-bit RAM control instructions only.

When the FMIF pin input signal is selected, the signal is divided by 2. When the AMIF pin input signal is

directly connected to the IFC, it is not divided.

By setting the IFMOD register, the gate is opened for 1-ms, 4-ms, or 8-ms periods. During the open period of

the gate, input frequency is counted by the 16-bit counter. When the gate is closed, the counting operation is

complete, and an interrupt is generated.