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FAN6210MY Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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FAN6210MY Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 11 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6210 Rev. 1.0.1 5 Electrical Characteristics VDD=20V, TA=25℃, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VDD DC Supply Voltage 7 24 V VDD-ON Turn-On Threshold Voltage 9 10 11 V VTH-OFF Turn-Off Threshold Voltage 7 8 9 V VDD-OVP VDD Over-Voltage Protection (OVP) 23.0 25.5 28.0 V VDD-OVP-HYS Hysteresis voltage for VDD OVP 0.3 0.8 1.3 V tOVP VDD OVP Debounce Time 250 μs SIN Section VSIN Logic Input Voltage 10.5 24.5 V tDLY_OUTH Delay Time Between SIN-HIGH and SOUT-HIGH 240 300 350 ns tDLY_OUTL Delay Time Between SIN-LOW and SOUT-LOW 75 100 150 ns tON_MAX SOUT Maximum On Time and Stop XP Pulse 8.5 10.0 12.0 μs DET Section VDET_H Detect Input Voltage to Send XP After SOUT Falling 2.5 3.0 3.5 V VDET_L Voltage to Drive XP Signal After SOUT Falling 1.5 2.0 2.5 V tPD_DET Delay Time to Send XP 30 50 100 ns XP XN Section tPLS_XN High-Level Pulsewidth of XN Signal 250 300 350 ns tPLS_XP High-Level Pulsewidth of XP Signal 600 700 800 ns tPD_XN Delay Time to Trigger XN by SIN Rising or Falling Edge 25 50 75 ns DPLS_OFF SIN Duty Ratio Shorter than DPLS_OFF Stop XP Pulse 10 % VXN XN Signal Output Voltage Level 5.5 8.0 V VXP XP Signal Output Voltage Level 5.5 8.0 V tR_XP XP Rising Time VDD = 15V; CL = 100pF; SOUT= 1V to 6V 30 ns tF_XP XP Falling Time VDD = 15V; CL = 100pF; SOUT= 7V to 2V 30 ns RDLY Section VRDLY RDLY Voltage RRDLY=24kΩ 1.08 1.20 1.32 V tDLY_XP Delay Time to Trigger XP by SOUT Rising Edge RRDLY=24kΩ 280 340 400 ns VZ Output Voltage Maximum (Clamp) VDD=25V 18.5 V VOL Output Voltage LOW VDD=15V; IO = 50mA 1.5 V VOH Output Voltage HIGH VDD=15V; IO = 50mA 10 V tR SOUT Rising Time VDD = 15V; CL = 5nF; SOUT= 2V to 9V 30 70 120 ns tF SOUT Falling Time VDD = 15V; CL = 5nF; SOUT= 9V to 2V 30 50 100 ns |
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Similar Description - FAN6210MY |
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