© 2009 Fairchild Semiconductor Corporation

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FAN6210 Rev. 1.0.1

3

Marking Information

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin #

Name

Description

1

XN

Pulse signal output terminal for SR off control signal.

2

XP

Pulse signal output terminal for SR on control signal.

3

SIN

Input signal for high- and low-side gate driver outputs.

4

RDLY

Delay time setting. This delay time is SOUT rising to trigger XP pulse delay time.

5

DET

Sensing freewheel diode voltage.

6

VDD

The power supply pin.

7

SOUT

Gate driving to high- and low-side gate driver.

8

GND

Ground.

F:

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