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AD8155 Datasheet(PDF) 31 Page - Analog Devices

Part No. AD8155
Description  6.5 Gbps Dual Buffer Mux/Demux
Download  36 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD8155 Datasheet(HTML) 31 Page - Analog Devices

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AD8155
Rev. 0 | Page 31 of 36
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The high speed differential inputs and outputs should be routed
with 100 Ω controlled impedance differential transmission
lines. The transmission lines, either microstrip or stripline,
should be referenced to a solid low impedance reference plane.
An example of a PCB cross-section is shown in Figure 48. The
trace width (W), differential spacing (S), height above reference
plane (H), and dielectric constant of the PCB material determine
the characteristic impedance. Adjacent channels should be kept
apart by a distance greater than 3 W to minimize crosstalk.
PCB DIELECTRIC
SIGNAL (MICROSTRIP)
SOLDERMASK
PCB DIELECTRIC
PCB DIELECTRIC
PCB DIELECTRIC
REFERENCE PLANE
REFERENCE PLANE
SIGNAL (STRIPLINE)
W
S
W
H
W
S
W
Figure 48. Example of a PCB Cross-Section
Thermal Paddle Design
The LFCSP is designed with an exposed thermal paddle to
conduct heat away from the package and into the PCB. By
incorporating thermal vias into the PCB thermal paddle,
heat is dissipated more effectively into the inner metal layers
of the PCB. To ensure device performance at elevated
temperatures, it is important to have a sufficient number of
thermal vias incorporated into the design. An insufficient
number of thermal vias results in a θJA value larger than
specified in Table 1. Additional PCB footprint and assembly
guidelines are described in the AN-772 Application Note, A
Design and Manufacturing Guide for the Lead Frame Chip Scale
Package (LFCSP).
It is recommended that a via array of 4 × 4 or 5 × 5 with a
diameter of 0.3 mm to 0.33 mm be used to set a pitch between
1.0 mm and 1.2 mm. A representative of these arrays is shown in
Figure 49.
THERMAL
VIA
THERMAL
PADDLE
Figure 49. PCB Thermal Paddle and Via
Stencil Design for the Thermal Paddle
To effectively remove heat from the package and to enhance
electrical performance, the thermal paddle must be soldered
(bonded) to the PCB thermal paddle, preferably with minimum
voids. However, eliminating voids may not be possible because
of the presence of thermal vias and the large size of the thermal
paddle for larger size packages. Also, outgassing during the
reflow process may cause defects (splatter, solder balling) if the
solder paste coverage is too big. It is recommended that smaller
multiple openings in the stencil be used instead of one big
opening for printing solder paste on the thermal paddle region.
This typically results in 50% to 80% solder paste coverage.
Figure 50 shows how to achieve these levels of coverage.
Voids within solder joints under the exposed paddle can have
an adverse affect on high speed and RF applications, as well as
on thermal performance. Because the LFCSP package incor-
porates a large center paddle, controlling solder voiding within
this region can be difficult. Voids within this ground plane can
increase the current path of the circuit. The maximum size for a
void should be less than via pitch within the plane. This assures
that any one via is not rendered ineffectual when any void
increases the current path beyond
the distance to the next available via.


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