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AD8155 Datasheet(PDF) 16 Page - Analog Devices

Part No. AD8155
Description  6.5 Gbps Dual Buffer Mux/Demux
Download  36 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD8155 Datasheet(HTML) 16 Page - Analog Devices

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AD8155
Rev. 0 | Page 16 of 36
Table 6. Features Available Through Toggle Pin or Serial Control
Feature
Pin Control
Serial Control
Switch Features
BICAST
One pin
One bit
A/B Lane Select
Two pins
Two bits
Loopback
Three pins
Three bits
Rx Features
EQ Levels
Two settings
10 settings
N/P Swap
Not available
Available
Squelch
Enabled
Three bits
Tx Features
Programmable Output Levels
±400 mV diff fixed1
±200 mV diff/±300 mV diff/±400 mV diff/±600 mV diff
PE Levels
Two settings
>7 settings
1 ±400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet
both in terms of the differentially measured voltage range (±400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted as mV p-p diff. An
output level setting of ±400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.
THE SWITCH
(MUX/DEMUX/UNICAST/BICAST/LOOPBACK)
The mux and demux functions of the AD8155 can be controlled
either with the toggle pins or through the register map. The
multiplexer path switches received data from Input Port A or
Input Port B to Output Port C. The SEL[1:0] pins allow switching
lanes independently. The demultiplexer path switches received
data from Input Port C to Output Port A, Output Port B, or (if
bicast mode is enabled) to both Output Port A and Output Port B.
Table 7. Port Selection and Configuration with All
Loopbacks Disabled
BICAST
SELx
Output
Port A
Output
Port B
Output
Port C
0
0
Ix_C[1:0]
Idle
Ix_A[1:0]
0
1
Idle
Ix_C[1:0]
Ix_B[1:0]
1
0
Ix_C[1:0]
Ix_C[1:0]
Ix_A[1:0]
1
1
Ix_C[1:0]
Ix_C[1:0]
Ix_B[1:0]
When the device is in unicast mode, the output lanes on either
Port A or Port B are in an idle state. In the idle state, the
transmitter output current is set to 0, and the P and N sides of
the lane are pulled up to the output termination voltage through
the on-chip termination resistors. To save power, the unused
receiver automatically disables.
The AD8155 supports port-level loopback, illustrated in Figure 36.
The loopback control pins override the lane select (SEL[1:0])
and bicast control (BICAST) pin settings at the port level. In serial
control mode, Bits [6:4] of Register 0x01 control loopback and
are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C.
Table 8 summarizes the different loopback configurations.
The loopback feature is useful for system debug, self-test, and
initialization, allowing system ASICs to compare Tx and Rx
data sent over a single bidirectional link. Loopback can also be
used to configure the device as a two- to six-lane receive
equalizer or backplane redriver.


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