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AD8155 Datasheet(PDF) 1 Page - Analog Devices |
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AD8155 Datasheet(HTML) 1 Page - Analog Devices |
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6.5 Gbps Dual Buffer Mux/Demux AD8155 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. FEATURES Dual 2:1 mux/1:2 demux Optimized for dc to 6.5 Gbps NRZ data Per-lane P/N pair inversion for routing ease Programmable input equalization Compensates up to 40 inches of FR4 Loss-of-signal detection Programmable output preemphasis up to 12 dB Programmable output levels with squelch and disable Accepts ac-coupled or dc-coupled differential CML inputs 50 Ω on-chip termination 1:2 demux supports unicast or bicast operation Port-level loopback Port or single lane switching 1.8 V to 3.3 V flexible core supply User-settable I/O supply from VCC to 1.2 V Low power, typically 2.0 W in basic configuration 64-lead LFCSP −40°C to +85°C operating temperature range APPLICATIONS Low cost redundancy switch SONET OC48/SDH16 and lower data rates RXAUI, 4× Fibre Channel, Infiniband, and GbE over backplane OIF CEI 6.25 Gbps over backplane Serial data-level shift 2-/4-/6-lane equalizers or redrivers FUNCTIONAL BLOCK DIAGRAM Ix_B[1:0] Ox_B[1:0] TRANSMIT PRE- EMPHASIS DUAL 2:1 MULTIPLEXER/ 1:2 DEMULTIPLEXER RECEIVE EQUALIZATION CONTROL LOGIC TRANSMIT PRE- EMPHASIS RECEIVE EQUALIZATION Ox_C[1:0] Ix_C[1:0] LB_A Ox_A[1:0] Ix_A[1:0] EQ 2:1 EQ EQ 1:2 LB_B LB_C PE_A PE_B PE_C EQ_A EQ_B EQ_C SEL[1:0] BICAST SEL4G LOS_INT AD8155 RESET I2C CONTROL LOGIC SCL SDA I2C_A[2:0] Figure 1. GENERAL DESCRIPTION The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output preemphasis, programmable output levels, and loss-of- signal detection. The nonblocking switch core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew. The main application of the AD8155 is to support redundancy on both the backplane and the line interface sides of a serial link. The demultiplexing path implements unicast and bicast capability, allowing the part to support either 1 + 1 or 1:1 redundancy. The AD8155 is also suited for testing high speed serial links because of its ability to duplicate incoming data. In a port- monitoring application, the AD8155 can maintain link connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B. The rich feature set of the AD8155 can be controlled either through external toggle pins or by setting on-chip control registers through the I2C® interface. |
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