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AD7357YRUZ Datasheet(PDF) 18 Page - Analog Devices

Part No. AD7357YRUZ
Description  Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7357YRUZ Datasheet(HTML) 18 Page - Analog Devices

 
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AD7357
Rev. 0 | Page 18 of 20
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial inter-
facing to the AD7357. The serial clock provides the conversion
clock and controls the transfer of information from the AD7357
during conversion. There is a single sample delay in the result
that is clocked out from the AD7357.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 16 SCLKs to complete. When 16
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
at Point B. On the rising edge of
Figure 30
CS, the conversion is terminated
and SDATAA and SDATAB go back into three-state. If CS is not
brought high but is, instead, held low for an additional 16 SCLK
cycles on SDATA , the data from the conversion on ADC B
is output on SDATAA.
Likewise, if CS is held low for an additional 16 SCLK cycles on
SDATAA, the data from the conversion on ADC A is output
on SDATAB (see
). In this case, the SDATA line in use
goes back into three-state on the 32nd SCLK falling edge or the
rising edge of
Figure 31
CS, whichever occurs first.
A minimum of 16 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7357. Note that the data that is
accessed on SDATAA and SDATAB is the result of the previous
conversion. CS going low provides the leading zero to be read
in by the microcontroller or DSP. The remaining data is then
clocked out by subsequent SCLK falling edges, beginning with
a second leading zero. Thus, the first falling clock edge on the
serial clock has the leading zero provided and also clocks out
the second leading zero. The 14-bit result then follows with the
final bit in the data transfer valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge. In applica-
tions with a slower SCLK, it may be possible to read in data on
each SCLK rising edge depending on the SCLK frequency. The
first rising edge of SCLK after the CS falling edge has the second
leading zero provided, and the 15th rising SCLK edge has DB0
provided.
A
CS
SCLK
1
5
15
16
SDATAA
SDATAB
2 LEADING ZEROS
THREE-
STATE
t4
2
34
t5
t3
tQUIET
t2
THREE-STATE
DB13
DB12
DB2
DB0
0
t6
t7
t8
0
0
DB1
DB11
DB10
t9
tACQUISITION
tCONVERT
B
Figure 30. Serial Interface Timing Diagram
CS
SCLK
1
5
16
SDATAA
THREE-
STATE
t4
2
34
17
t5
t3
t2
THREE-
STATE
t6
t7
15
0
0
0
DB12B
DB1B
DB0B
0
18
32
31
DB13A
2 LEADING
ZEROS
DB12A
DB11A
DB0A
DB13B
0
2 ZEROS
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs


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