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AD7357YRUZ Datasheet(PDF) 15 Page - Analog Devices

Part No. AD7357YRUZ
Description  Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
Download  20 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com

AD7357YRUZ Datasheet(HTML) 15 Page - Analog Devices

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Rev. 0 | Page 15 of 20
The AD7357 mode of operation is selected by controlling the
logic state of the CS signal during a conversion. There are three
possible modes of operation: normal mode, partial power-down
mode, and full power-down mode. After a conversion has been
initiated, the point at which CS is pulled high determines which
power-down mode, if any, the device enters. Similarly, if already
in a power-down mode, CS can control whether the device
returns to normal operation or remains in a power-down mode.
These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for the differing
application requirements.
Normal mode is intended for applications needing the fastest
throughput rates. The user does not have to worry about any
power-up times because the AD7357 remains fully powered at
all times. Figure 24 shows the general diagram of the operation
of the AD7357 in this mode.
Figure 24. Normal Mode Operation
The conversion is initiated on the falling edge of CS, as described
in the
section. To ensure that the part remains
fully powered up at all times,
Serial Interface
CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge
but before the 16th SCLK falling edge, the part remains powered
up, but the conversion is terminated and SDATA and SDATAB
go back into three-state. 16 serial clock cycles are required to
complete the conversion and access the conversion result for
the AD7357. The SDATA lines do not return to three-state
after 16 SCLK cycles have elapsed, but instead do so when
is brought high again. If CS is left low for another 2 SCLK
cycles, two trailing zeros are clocked out after the data. If CS
is left low for a further 16 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line as
shown in
(see the
Figure 31
Serial Interface
When 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32nd SCLK falling edge. If CS is brought high
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion, if so desired,
because the bus still returns to three-state upon completion of
the dual result read.
When a data transfer is complete and SDATAA and SDATAB
have returned to three-state, another conversion can be initiated
after the quiet time, tQUIET, has elapsed by bringing CS low again
(assuming the required acquisition time has been allowed).
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered
down between each conversion, or a series of conversions
can be performed at a high throughput rate and the ADC is
then powered down for a relatively long duration between
these bursts of several conversions. When the AD7357 is in
partial power-down, all analog circuitry is powered down
except for the on-chip reference and reference buffers.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the
second falling edge of SCLK and before the 10th falling edge of
SCLK, as shown in
. When
Figure 25
CS is brought high in this
window of SCLKs, the part enters partial power-down mode,
the conversion that was initiated by the falling edge of CS is
terminated, and SDATA and SDATAB go back into three-state. If
CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
Figure 25. Entering Partial Power-Down Mode
To exit this mode of operation and to power up the AD7357
again, perform a dummy conversion. On the falling of CS, the
device begins to power up and continues to power up as long
as CS is held low until after the falling edge of the 10th SCLK.
The device is fully powered up after approximately 200 ns
elapses (or one full conversion), and valid data results from the
next conversion, as shown in
. If
Figure 26
CS is brought high
before the second falling edge of SCLK, the AD7357 again goes
into partial power-down mode. This avoids accidental power-
up due to glitches on the CS line. Although the device may
begin to power up on the falling edge of CS, it powers down
again on the rising edge of CS. If the AD7357 is already in
partial power-down mode and CS is brought high between
the second and 10th falling edges of SCLK, the device enters
full power-down mode.

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