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AD7357YRUZ Datasheet(PDF) 5 Page - Analog Devices

Part No. AD7357YRUZ
Description  Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7357YRUZ Datasheet(HTML) 5 Page - Analog Devices

 
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AD7357
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
500
kHz min
80
MHz max
tCONVERT
t2 + 15.5 × tSCLK
ns min
tSCLK = 1/fSCLK
tQUIET
5
ns min
Minimum time between end of serial read and next falling edge of CS
t2
5
ns min
CS to SCLK setup time
t32
6
ns max
Delay from CS until SDATAA and SDATAB are three-state disabled
t42, 3
Data access time after SCLK falling edge
12.5
ns max
1.8 V ≤ VDRIVE < 2.25 V
11
ns max
2.25 V ≤ VDRIVE < 2.75 V
9.5
ns max
2.75 V ≤ VDRIVE < 3.3 V
9
ns max
3.3 V ≤ VDRIVE ≤ 3.6 V
t5
5
ns min
SCLK low pulse width
t6
5
ns min
SCLK high pulse width
t72
SCLK to data valid hold time
3.5
ns min
1.8 V ≤ VDRIVE < 2.75 V
3
ns min
2.75 V ≤ VDRIVE ≤ 3.6 V
t8
9.5
ns max
CS rising edge to SDATA , SDATAB, high impedance
A
t9
5
ns min
CS rising edge to falling edge pulse width
t102
4.5
ns min
SCLK falling edge to SDATAA, SDATAB, high impedance
9.5
ns max
SCLK falling edge to SDATAA, SDATAB, high impedance
Latency
1 conversion latency
1 Temperature ranges are as follows: Y grade: −40°C to +125°C, B grade: −40°C to +85°C.
2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB.
3 The time required for the output to cross 0.4 V or 2.4 V.


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