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SMX55161A-80HKCM Datasheet(PDF) 5 Page - Austin Semiconductor |
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SMX55161A-80HKCM Datasheet(HTML) 5 Page - Austin Semiconductor |
5 / 64 page VRAM SM55161A Production Austin Semiconductor, Inc. AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice. 5 SMJ55161A Rev. 1.6 03/05 TABLE 1: DRAM & SAM FUNCTIONS CASx\ FALL CASx\ 2 TRG\ WE\ DSF DSF RAS\ CASX\ 3 RAS\ CASL\ CASU\ WE\ Reserved (do not use) L L L L X X X X X --- CBR refresh (no reset) and stop- point set 4 LX L H X Stop point 5 X X X CBRS CBR refresh (option reset) 6 L X H L X X X X X CBR CBR refresh (no reset) 7 L X H H X X X X X CBRN Full-register-transfer read H L H L X Row Address Tap Point XX RT Split-register-transfer read H L H H X Row Address Tap Point X X SRT DRAM write (nonpersistent write-per-bit) H H LLL Row Address Column Address Write Mask Valid Data RWM DRAM block write (nonpersistent write-per-bit) HH L L H Row Address Block Address A3-A8 Write Mask Column Mask BWM DRAM write (persistent write-per-bit) H H LLL Row Address Column Address X Valid Data RWM DRAM block write (persistent write-per-bit) HH L L H Row Address Block Address A3-A8 X Column Mask BWM DRAM write (nonmasked) H H H L L Row Address Column Address X Valid Data RW DRAM block write (nonmasked) H H H L H Row Address Block Address A3-A8 X Column Mask BW Load write-mask register 8 H HHH L Refresh Address XX Write Mask LMR Load color register H HHHH Refresh Address XX Color Data LCR Masked Write Transfer 9 H LLL X Row Address Tap Point Write Mask X MWT Masked Split Write Transfer 9 HL L H X Row Address Tap Point Write Mask X MSWT Masked Flash Write Transfer 9 HH L H X Row Address X Write Mask --- FWM MNE CODE FUNCTION RAS\ FALL ADDRESS DQ0-DQ15 1 LEGEND: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t Care NOTES: 1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later. 2. Logic L is selected when either or both CASL\ and CASU\ are low. 3. The column address and block address are latched on the first falling edge of CASx\. 4. CBRS cycle should be performed immediately after the power-up initialization cycle. 5. A0–A3, A8: don’t care; A4–A7: stop-point code 6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. 7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. 8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. 9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write. |
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