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AS5SP1M18DQ Datasheet(PDF) 3 Page - Austin Semiconductor
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AS5SP1M18DQ Datasheet(HTML) 3 Page - Austin Semiconductor
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Revision 1.0 04/04/04
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Austin Semiconductor, Inc.
Austin Semiconductor’s AS5SP1M18DQ Synchronous SRAM is
manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including those
Synchronous SRAM READ and WRITE operations as well as
Synchronous Burst READ/WRITE operations.
All inputs with
the exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices input
The type, start and the duration of Burst Mode
operations is controlled by MODE, ADSC\, ADSP\ and ADV as
well as the Chip Enable pins CE1\, CE2, and CE3\.
synchronous accesses including the Burst accesses are enabled via
the use of the multiple enable pins and wait state insertion is
supported and controlled via the use of the Advance control
The ASI AS5SP1M18DQ supports both Interleaved as well as
Linear Burst modes therefore making it an architectural fit for
either the Intel or Motorola CISC processor elements available on
the Market today.
The AS5SP1M18DQ supports Byte WRITE operations and enters
this functional mode with the Byte Write Enable (BWE\) and the
Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global
Writes are supported via the Global Write Enable (GW\) and
Global Write Enable will override the Byte Write inputs and will
perform a Write to all Data I/Os.
The AS5SP1M18DQ provides ease of producing very dense
arrays via the multiple Chip Enable input pins and Tri-state
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: 
ADSP\ pr ADSC\ is asserted LOW,  Chip Enables are all
asserted active, and  the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
The address presented to the Address inputs is stored within the
Address Registers and Address Counter/Advancement Logic and
then passed or presented to the array core. The corresponding
data of the addressed location is propagated to the Output
Registers and passed to the data bus on the next rising clock via
the Output Buffers. The time at which the data is presented to the
Data bus is as specified by either the Clock to Data valid
specification or the Output Enable to Data Valid spec for the
device speed grade chosen. The only exception occurs when the
device is recovering from a deselected to select state where its
outputs are tristated in the first machine cycle and controlled by
its Output Enable (OE\) on following cycle. Consecutive single
cycle READS are supported. Once the READ operation has been
completed and deselected by use of the Chip Enable(s) and either
ADSP\ or ADSC\, its outputs will tri-state immediately.
A Single ADSP\ controlled WRITE operation is initiated when
both of the following conditions are satisfied at the time of Clock
(CLK) HIGH:  ADSP\ is asserted LOW, and  Chip
Enable(s) are asserted ACTIVE.
The address presented to the
address bus is registered and loaded on CLK HIGH, then
presented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
ignored on the first machine cycle.
ADSP\ triggered WRITE
accesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the data
presented to the array via the Data bus will be written into the
array at the corresponding address location specified by the
Address bus. If GW\ is HIGH (inactive) then BWE\ and one or
more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\)
controls the write operation. All WRITES that are initiated in this
device are internally self timed.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satisfied:  ADSC\ is asserted
LOW,  ADSP\ is de-asserted (HIGH),  Chip Enable(s) are
asserted (TRUE or Active), and  the appropriate combination
of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s) or
the complete data-path.
ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of clock
HIGH will be the location that the WRITE occurs. The ADV pin
is ignored during this cycle, and the data WRITTEN to the array
will either be a BYTE WRITE or a GLOBAL WRITE depending
on the use of the WRITE control functions GW\ and BWE\ as
well as the individual BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP1M18DQ has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous input
and asserting this pin places the SSRAM in a deep power-down
mode (SLEEP). White in this mode, Data integrity is guaranteed.
For the device to be placed successfully into this operational
mode the device must be deselected and the Chip Enables, ADSP\
and ADSC\ remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Use of this deep power-down mode
conserves power and is very useful in multiple memory page
designs where the mode recovery time can be hidden.
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