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AS5SP1M18DQ Datasheet(PDF) 1 Page - Austin Semiconductor

Part No. AS5SP1M18DQ
Description  Plastic Encapsulated Microcircuit 18Mb, 1M x 18, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
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Maker  AUSTIN [Austin Semiconductor]
Homepage  http://www.austinsemiconductor.com
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AS5SP1M18DQ Datasheet(HTML) 1 Page - Austin Semiconductor

 
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AS5SP1M18DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 04/04/04
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
1
COTS PEM
AS5SP1M18DQ
Austin Semiconductor, Inc.
SSRAM
Parameter
Symbol
200Mhz
166Mhz
133Mhz
Units
Cycle Time
tCYC
5.0
6.0
7.5
ns
Clock Access Time
tCD
3.0
3.5
4.0
ns
Output Enable Access Time
tOE
3.0
3.5
4.0
ns
Plastic Encapsulated Microcircuit
18Mb, 1M x 18, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
Features
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without Data
Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
Fast Access Times
Block Diagram
General Description
ASI’s AS5SP1M18DQ is a 18Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature screening
levels, fabricated using High Performance CMOS technology and
is organized as a 1M x 18. It integrates address and control
registers, a two (2) bit burst address counter supporting four (4)
double-word transfers.
Writes are internally self-timed and
synchronous to the rising edge of clock.
ASI’s
AS5SP1M18DQ
includes
advanced
control
options
including Global Write, Byte Write as well as an Asynchronous
Output enable.
Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\.
Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs.
Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
Memory Array
x18
SBP
I/O Gating and Control
Output
Register
Input
Register
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
DQx, DQPx
Output
Driver
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
OE\
ZZ
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
DQb
DQb
NC
NC
NC
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
A
NC
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VDD
NC
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
SSRAM [SPB]
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
ZZ
30
29
28
27
26
25
24
23
NC
NC
VDD
VSS
22
21
20
19
18
17
16
15
14
13
12
10
11
NC


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