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AS5SP1M18DQ Datasheet(PDF) 5 Page - Austin Semiconductor

Part No. AS5SP1M18DQ
Description  Plastic Encapsulated Microcircuit 18Mb, 1M x 18, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
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Maker  AUSTIN [Austin Semiconductor]
Homepage  http://www.austinsemiconductor.com
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AS5SP1M18DQ Datasheet(HTML) 5 Page - Austin Semiconductor

 
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AS5SP1M18DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 04/04/04
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
5
COTS PEM
AS5SP1M18DQ
Austin Semiconductor, Inc.
SSRAM
DC Electrical Characteristics (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Thermal Resistance
Notes:
[1]
All Voltages referenced to VSS (Logic Ground)
[2]
Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
[3]
MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
[4]
The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
[5]
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
[6]
This parameter is sampled
Symbol
Parameter
Test Conditions
Min
Max
Units
Notes
VDD
Power Supply Voltage
3.135
3.630
V
1
VDDQ
I/O Supply Voltage
2.375
VDD
V
1,5
VoH
Output High Voltage
VDD=Min., IOH=-4mA
3.3v
2.4
V
1,4
VDD=Min., IOH=-1mA
2.5v
2
V
1,4
VoL
Output Low Voltage
VDD=Min., IOL=8mA
3.3v
0.4
V
1,4
VDD=Min., IOL=1mA
2.5v
0.4
V
1,4
VIH
Input High Voltage
3.3v
2
VDD+0.3
V
1,2
2.5v
1.7
VDD+0.3
V
1,2
VIL
Input Low Voltage
3.3v
-0.3
0.8
V
1,2
2.5v
-0.3
0.7
V
1,2
IIL
Input Leakage (except ZZ)
VDD=Max., VIN=VSS to VDD
-5
5
uA
3
IZZL
Input Leakage, ZZ pin
-30
30
uA
3
IOL
Output Leakage
Output Disabled, VOUT=VSSQ to VDDQ
-5
5
uA
IDD
Operating Current
VDD=Max., f=Max.,
5.0ns Cycle, 200 Mhz
400
mA
IOH=0mA
6.0ns Cycle, 166 Mhz
350
mA
7.5ns Cycle, 133 Mhz
300
mA
ISB1
Automatic CE. Power-down
Max. VDD, Device De-Selected,
Current -TTL inputs
VIN>/=VIH or VIN</=VIL
5.0ns Cycle, 200 Mhz
100
mA
f=fMAX=1/tCYC
6.0ns Cycle, 166 Mhz
90
mA
7.5ns Cycle, 133 Mhz
85
mA
ISB2
Automatic CE. Power-down
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
70
mA
Current - CMOS Inputs
f=fMAX=1/tCYC
ISB4
Automatic CE. Power-down
Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0
80
mA
Current -TTL inputs
ISB3
Automatic CE. Power-down
Max. VDD, Device De-Selected, or
Current - CMOS Inputs
VIN</=0.3v or VIN >/=VDDQ-0.3v,
5.0ns Cycle, 200 Mhz
95
mA
f-Max=1/tCYC
6.0ns Cycle, 166 Mhz
85
mA
7.5ns Cycle, 133 Mhz
80
mA
Symbol
Description
Conditions
Typical
Units
Notes
Thermal Resistance
θθθθJA
(Junction to Ambient)
1-Layer
31
0C/W
6
Test Conditions follow standard test methods and
Thermal Resistance
procedures for measuring thermal impedance, as
θθθθJC
(Junction to Top of Case, Top) per EIA/JESD51
6
0C/W
6


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